1. Field of the Invention
This invention relates to a semiconductor memory device, particularly to a dynamic memory device including a storage capacitor and a switching transistor. More particularly, this invention relates to a dynamic type MOS random access memory device (which will be shortly referred to as "MOS.multidot.RAM") including an insulated-gate field effect transistor (which will also be shortly referred to as "MOS transistor") as the switching transistor.
2. Description of the Prior Art
As the MOS.multidot.RAM, there have been proposed a variety of modes including the minimum one-transistor type. In the conventional one-transistor type MOS.multidot.RAM, as shown in FIG. 1, a memory cell composed of an insulated-gate field effect switching transistor (which will be shortly referred to as "MOS transistor") 1 and a storage capacitor 2 for storing information is addressed by a word line made of an electrode of Al and by a data line made of a diffusion layer 4. Here: reference numeral 5 indicates an Si substrate; 6 an insulating layer (of SiO.sub.2 or the like) for isolating different elements from each other; 7 a gate insulating film (of SiO.sub.2, Al.sub.2 O.sub.3, Si.sub.3 N.sub.4 or the like); 8 a storage-gate electrode of a first level polycrystalline silicon layer; 9 an inter-layer insulating film (of SiO.sub.2 or the like); 10 a diffusion layer for constituting a source or drain together with the aforementioned diffusion layer 4; 11 an inversion layer which is formed by impressing a voltage upon the polycrystalline silicon electrode 8; and 12 a polycrystalline silicon electrode (or gate electrode). The aforementioned storage capacitor 2 includes an MIS (Metal-Insulator-Semiconductor) capacitor which is established between the polycrystalline silicon electrode 8 and the inversion layer 12.
As seen from FIG. 1, the storage capacitor 2 for storing information is two-dimentionally arranged on one plane together with the switching transistor 1 so that the memory cell has a large area. In the one-MOS transistor type RAM, the charge stored in the storage capacitor is proportional to the signals voltage, which is desired to be high for the circuit considered. In order to elongate the charge hold time thereby to ensure the stable operation of the circuit, therefore, the storage capacitance is also desired to be high. In order to increase the storage capacitance, however, the area of a capacitor portion has to be enlarged reducing the integration density.
In Japanese Laid-Open Patent Publication No. 53-4483 or U.S. Pat. No. 4,151,607, we have proposed a memory cell which is so constructed that the capacitor portions for storing the charge are stacked one on another so that the elements are positively utilized in the longitudinal direction thereof thereby to increase the integration density and accordingly the storage capacitance. FIG. 2 sectionally shows the construction of the one-MOS transistor RAM (which will be shortly referred to as "STC (Stacked Capacitor Structure) memory") using the stacked capacitor. As shown in FIG. 2, an inter-layer insulating film 14 for constituting the capacitor is mounted on the first level electrode (or, in this example, a voltage applying electrode for forming the inversion layer 11) 8 which is formed on the region (which resorts, in this example, to the inversion layer althrough the region of the opposite conductivity may be made of an impurity layer) 11 positioned adjacent to the diffusion layer 10 constituting the source or drain of the insulated-gate field effect switching transistor 1 while exhibiting the opposite conductivity to that of the substrate 5. Then, a second electrode 15 is mounted thereon such that its one end is connected with the diffusion layer 10.
After that, the inter-layer insulating film 9 and the Al electrode 3 providing the work line are mounted in a similar manner to the prior art.
Thus, the two electrodes 8 and 15 constitute an insulator capacitor C.sub.I through the inter-layer insulating film 14. The storage capacitance of the capacitor 2 is expressed by C.sub.I +C.sub.OX +C.sub.D. Here, letters C.sub.OX indicate the MIS capacitor which is constituted between the inversion layer 11 and the electrode 8 through an oxide film 7b, whereas letters C.sub.D indicate the depletion layer capacitor which is constituted between the inversion layer 11 and the substrate 5 through the depletion layer.
In other words, the memory cell can have its storage capacitance increased by the capacitance C.sub.I in comparison with the conventional value of C.sub.OX +C.sub.D by resorting to the construction that the electrode 15 is mounted through the insulating film 14 upon the electrode 8, as shown in FIG. 2. As a result, in case the same storage capacitance as that of the conventional memory cell is used, the area of the memory cell can be remarkably decreased.
In the STC memory thus constructed, the insulating film 14 constituting the storage capacitor can be arbitrarily addressed by stacking the capacitor portion upon the element with the resultant advantage that the film of Si.sub.3 N.sub.4 having high permitivity can be used.
In this STC memory, however, in case a thin film of Si.sub.3 N.sub.4 is used as the insulating film 14 with a view to increasing the storage capacitance, there is a limit to the increase in the storage capacitance due to the problem of a leakage current or the like. Moreover, since the diffusion layer 10 connected with one electrode of the storage capacitor is positioned to directly contact with the substrate 5 of low impurity concentration, extinction of the charge takes place due to the noises including a radioactive ray, thus causing a memory operation error which will influence the MIS capacitor C.sub.OX and the depletion layer capacitor C.sub.D.
As an improvement over the one-transistor type MOS.multidot.RAM shown in FIG. 1, on the other hand, there has also been proposed a buried capacitor type memory which is disclosed in Japanese Laid-Open Patent Publication No. 53-34435. The buried capacitor type memory disclosed resorts to the pn junction capacitor between a diffusion layer 13 constituting the source or drain of the insulated-gate field effect transistor 1 and a region 16 which is formed thereunder and which has the same conductivity type but a higher impurity concentration than the substrate 5, as shown in FIG. 3. The buried capacitor type memory thus disclosed has such a construction that the storage capacitor is buried in the substrate and provides a memory cell having a smaller area without any requirement for the multiple-layer interconnection technique because the electrode 8 is not used as contrary to the storage gate structure of the memory shown in FIG. 1.
In the buried capacitor type memory disclosed, however, the increase in the capacitance is restricted by the leakage current through and the breakdown voltage at the pn junction. Moreover, since the capacitance of the pn junction per unit area is lower than that of an oxide film or the like, the larger area is required for the higher storage capacitance, thus inviting a disadvantage in the integration density.